Jen-Chieh Hsueh | Hardware Security | Best Paper Award

Dr. Jen-Chieh Hsueh | Hardware Security | Best Paper Award

MediaTek, United States

Dr. Jen-Chieh (Jack) Hsueh  is an accomplished electrical engineer specializing in analog/RF circuit design , with expertise in advanced semiconductor technologies such as 22FDX and 6nm . He holds a Ph.D. from The Ohio State University and has hands-on experience in full analog IC design flow , including tape-out, DRC, LVS, and PEX . Currently a Staff Engineer at MediaTek , he contributes to next-gen Wi-Fi design with a focus on high-performance, low-power solutions . Passionate about circuit innovation and silicon security , Jack is open to relocation for impactful opportunities .

Profile

Scholar

🎓 Education:

Jack earned his Ph.D. in Electrical Engineering from The Ohio State University , where he developed a novel time-based sensor for IC authentication using BEOL resistance and capacitance . His dissertation combined sensor fabrication, compact modeling, and circuit analysis . He also holds an M.S. from National Taiwan University , where he designed a three-channel true-time delay beamforming front-end . Throughout his academic path, he completed coursework in RFICs, data converters, PLLs, and mixed-signal systems . His education bridges theory, modeling, and hands-on silicon prototyping .

💼 Experience:

Jack is currently a Staff Engineer at MediaTek (2023–present) , where he designed and simulated G-band Wi-Fi PADs in a 6nm process , optimizing performance and manufacturability. His prior work includes projects on ultra-low phase noise VCOs, high IIP2 mixers, and UWB LNAs using 22nm FDSOI technology . He has contributed to both system-level modeling and transistor-level implementation using tools like Cadence, Spectre-RF, EMX, MATLAB, and ADS . His broad circuit experience covers VCOs, mixers, TRNGs, and high-speed I/Os , preparing him for diverse analog/RF challenges.

🏆 Awards & Honors:

Jack’s work has been presented at leading conferences including PRIME 2024 and MWSCAS 2017 , and published in prestigious journals like Microelectronics Journal and Electronics Letters . His paper on ultra-low voltage chaos-based TRNGs for IoT is widely cited . While specific awards are not listed, his selection as Staff Engineer at MediaTek and mentorship under top advisors like Prof. Waleed Khalil and Prof. Liang-Hung Lu underscore his academic and industry recognition . His sensor research earned significant visibility in trusted computing circles .

🔬 Research Focus:

Jack’s research focuses on analog/RF circuit design , sensor development for device fingerprinting and process attestation , and secure silicon solutions for authentication and identification . He specializes in low-power, high-performance systems across wireless, mixed-signal, and cryptographic domains . His work intersects physical modeling, system-level simulation, and tape-out validation . With experience in advanced CMOS and FDSOI nodes, his research supports emerging needs in trusted electronics, 5G/6G communications, and hardware-level cybersecurity . He aims to bridge cutting-edge academic insight with real-world semiconductor innovation .

📝 Conclusion

Dr. Jen-Chieh (Jack) Hsueh is a strong candidate for a Best Paper Award, particularly in conferences or journals emphasizing analog/RF circuits, hardware security, or trusted silicon systems. His research combines innovative sensor design, silicon-level verification, and security relevance, aligning well with award criteria that value originality, rigor, and impact. With minor improvements in outreach, benchmarks, and application framing, his work could become a standout contribution in the field.

Publication

An ultra-low voltage chaos-based true random number generator for IoT applications
Authors: J.-C. Hsueh, V.H.-C. Chen
Journal: Microelectronics Journal
Year: 2019
Citations: 39

Instantaneous in-band radio frequency interference suppression using non-linear folders
Authors: E. Chen, J.-C. Hsueh, V. H.-C. Chen
Journal: Electronics Letters
Year: 2019
Citations: 2

An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI
Authors: J.-C. Hsueh, V. H.-C. Chen, J.-O. Plouchart
Conference: 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2017
Citations: 1